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| Technical Overview CD4000B Series This section is intended as a guide for circuit and equipment designers in the operation and application of MOS integrated circuits. It covers general operating and handling considerations with respect to the following critical factors: * Operating Supply Voltage Range * Power Dissipation and Derating * System Noise Considerations * Power Source Rules * Gate-oxide Protection Networks * Input Signals and Ratings * Chip www..com Assembly and Storage * Device Mounting * Testing More specific information is then given on significant features, special design and application requirements, and standard ratings and electrical characteristics for CMOS Bseries logic circuits, and on CMOS special function circuits (special interface and display driver circuits). Dynamic power dissipation has three components: 1. The dissipation that results from current that charges and discharges the external load capacitance of the output buffers. The dissipation of each output buffer is equal to CV2f, where C is the load capacitance, V is the supply voltage, and f is the switching frequency of that output. 2. The dissipation that results from current that charges and discharges the internal node capacitances. 3. The dissipation caused by the current spikes through the PMOS and NMOS transistors in series at the instant of switching. This component amounts to approximately 10% of the total dissipation, shown graphically in the datasheets of most CMOS circuits. All CMOS devices are rated at 200mW per package at the maximum operating ambient temperature rating (TA) of 125oC for all packages. Power ratings for temperatures below the maximum operating temperature are shown in the standard CMOS thermal derating chart in Figure 1. This chart assumes that the device is mounted and soldered (or placed in a socket) on a PC board; there is natural convection cooling, with the PC board mounted horizontally; and the pressure is standard (14.7psia). In addition to the overall package dissipation, device dissipation per output transistor is limited to 100mW maximum over the full package operating temperature range. General Operating and Handling Considerations The following paragraphs discuss some key operating and handling considerations that must be taken into account to achieve maximum advantage of the CMOS technology. Additional information on the operation and handling of CMOS integrated circuits is given in Application Note AN6525, "Guide to Better Handling and Operation of CMOS Integrated Circuits". See Section 8, "How to Use AnswerFAX", in this selection guide. Operating Supply Voltage Range Because logic systems occasionally experience transient conditions on the power supply line which, when added to the nominal power-bus voltage, could exceed the safe limits of circuits connected to the power bus, the recommended operating supply voltage range is 3V to 18V for B-series devices. The recommended maximum power supply limit is substantially below the minimum primary breakdown limit for the devices to allow for limited power supply transient and regulation limits. For circuits that operated in a linear mode over a portion of the voltage range, such as RC or crystal oscillators, a minimum supply voltage of 4V is recommended. Power Dissipation and Derating The power dissipation of a CMOS integrated circuit is the sum of a DC (quiescent) component and an AC (dynamic) components. The DC component is the sum of the net integrated circuit reverse diode junction current and the surface leakage current times the supply voltage. In standard Bseries logic devices, the DC dissipation typically ranges, depending upon device complexity, from 100nW to 400nW for a supply voltage of 10V. Worst-case DC dissipation is the product of the maximum quiescent current (given in the data sheet on each device) and the DC supply voltage VDD . PACKAGE DISSIPATION (mW) SLOPE = 12mW/oC 600 500 400 300 200 100 20 40 60 80 85 100 (oC) 120 125 TA , AMBIENT TEMPERATURE FIGURE 1. STANDARD CMOS THERMAL DERATING CHART System Noise Considerations In general, CMOS devices are much less sensitive to noise on power and ground lines than bipolar logic families (such as TTL or DTL). However, this sensitivity varies as a function of the power supply voltage, and more importantly as a function of synchronism between noise spikes and input transitions. Good power distribution in digital systems requires that the power bus have a low dynamic impedance; for this purpose, discrete decoupling capacitors should be distributed across the power bus. A more detailed discussion of CMOS noise immunity is provided by Application Note AN6587, "Noise Immunity of B-series CMOS Integrated Circuits". See Section 8, "How to Use AnswerFAX", in this selection guide. 5-3 Technical Overview Power Source Rules Figure 2 shows the basic CMOS inverter and its gate-oxide protection network plus inherent diodes. The safe operating procedures listed below can be understood by reference to this inverter. VDD (NOTE 1) D2 IN COS/MOS R1 D1 D1 (NOTE 1) D1 D1 OUT (NOTE 1) OUT D2 D2 R2 IN D1 (NOTE 1) and/or P-N junctions. Figure 3 shows the gate-oxide protection circuits used to protect CMOS devices from static electricity damage. Application Note AN6525, "Guide to Better Handling and Operation of CMOS Integrated Circuits". See Section 8, "How to Use AnswerFAX", in this selection guide. VDD VSS NOTES: www..com 1. These Diodes are inherently part of the manufacturing process. 2. Diode Breakdown D1 25V D2 50V R2 << R1 FIGURE 2. BASIC CMOS INVERTER WITH B-SERIES TYPE PROTECTION NETWORK VSS FIGURE 3A. FOR B-SERIES CMOS PRODUCT VDD (NOTE 2) CD4049UB 1. When separate power supplies are used for the CMOS device and for the device inputs, the device power supply should always be turned on before the independent input signal sources, and the input signals should be turned off before the power supply is turned off (VSS VI VDD as a maximum limit). This rule will prevent over dissipation and possible damage to the D2 input protection diode when the device power supply is grounded. When the device power supply is an open circuit, violation of this rule can result in undesired circuit operation although device damage should not result: AC inputs can be rectified by diode D2 to act as a power supply. 2. The power supply operating voltage should be kept safely below the absolute maximum supply rating, as indicated previously. 3. The power supply polarity for CMOS circuits should not be reversed. The positive (VDD) terminal should never be more than 0.5V negative with respect to the negative (VSS) terminal (VDD - VSS > -0.5V). Reversal of polarities will forward-bias and short the structural and protection diode between VDD and VSS. 4. VDD should be equal to or greater than VCC for CMOS buffers which have two power supplies (except for the CD40109B, and in particular, for CD4009 and CD4010 CMOS-to-TTL "down" conversion devices). 5. Power source current capability should be limited to as low a value as reasonable to assure good logic operation. 6. Large values of resistors in series with VDD or VSS should be avoided; transient turn-on of input protection diodes can result from drops across such resistors during switching. Gate-Oxide Protection Network A problem occasionally encountered in handling and testing low power semiconductor devices, including MOS and small geometry bipolar devices, has been damage to gate oxide IN (NOTE 1) OUT (NOTE 1) CD4050B CD40109B VSS FIGURE 3B. FOR CD4049UB AND CD4050B AND CD40109B CMOS TYPES GATE 1 D1 (NOTE 1) VDD IN/OUT D2 (NOTE 1) P-WELL N-SUB (NOTE 1) D1 OUT/IN VSS (NOTE 1) D2 GATE 2 FIGURE 3C. FOR CMOS TRANSMISSION GATES NOTES: 1. These Diodes are inherently part of the manufacturing process. 2. VCC for CD4049UB and CD4050B 3. Diode Breakdown D1 25V D2 50V FIGURE 3. GATE-OXIDE PROTECTION NETWORKS USED IN HARRIS CMOS INTEGRATED CIRCUITS 5-4 Technical Overview Input Signals and Ratings Input signals should be maintained with in the power supply voltage range, VSS VI VDD . If the input signal exceeds the recommended input signal swing range, the input current should be limited to 100A to minimize cross talk between input signals on adjacent terminals, and also to minimize any reduction in noise immunity. The absolute maximum input current rating of 10mA, shown in the published data, protects the device against the possible occurrence of an induced VDD - VSS latch condition, or damage to the input protection diodes. Latch-up conditions are explained in Application Note AN6525, "Guide to Better Handling and Operation of CMOS Integrated Circuits". See Section 8, "How to Use AnswerFAX", in this selection guide. www..com 7. Output transistors may be over dissipated by operating buffers as linear amplifiers or using these types as one shot or astable multivibrators. Noise immunity and Noise Margin The complementary structure of the inverter, common to all CMOS logic devices, results in a near-ideal input-output transfer characteristic, with switching point midway (45% to 55%) between the 0 and 1 output logic levels. The result is high DC noise immunity. Figure 4 shows a typical transfer curve that may be used to define the DC noise immunity of CMOS integrated circuits. The noise immunity voltage (VIL or VIH) is the noise voltage at any one input that does not propagate through the system. Minimum noise immunity for buffered B-series CMOS devices is 30%, 30%, and 27%, respectively for supply voltages VDD of 5V, 10V, 15V and 20% of VDD for all unbuffered gates. The VIL and VIH specifications define the maximum permissible additive noise voltage at an input terminal when input signals are within 50mV of the supply rails. VIL (TYP) 10 VO(HIGH) 9 8 7 6 5 4 3 2 1 0 1 2 34 5 VIN 6 ALL CMOS inputs should be terminated. An exception can be made in the case of unbuffered NOR and NAND gates where terminating one of the series inputs to the proper polarity will not permit current flow caused by a floating input. Thus tying low one of the inputs of an unbuffered NAND gate, or tying high one of the inputs of an unbuffered NOR gate will satisfy this requirement. When CMOS inputs are wired to edge card connectors with CMOS drive coming from another PC board, a shunt resistor in the range of 100kW should be connected to VDD or VSS , as applicable, in case the inputs become unterminated with the power supply on. When CMOS circuits are driven by TTL logic, a "pull-up" resistor should be connected from the CMOS input to 5V (further information is given in Application Note AN6602, "Interfacing COS/MOS with Other Logic Families", See Section 8, "How to Use AnswerFAX", in this selection guide. Output Rules 1. The power dissipation in a CMOS package should not exceed the rated value for the ambient temperature specified. The actual dissipation should be calculated when shorting outputs directly to VDD or VSS , driving low impedance loads, or directly driving the base of P-N-P or N-P-N bipolar transistor. VNML = VIL (MAX) - VO(LOW) VNML = VO(HIGH) - VIH (MIN) VIH TYP VOUT VO(LOW) 7 8 9 10 VIL MAX VIH MIN FIGURE 4. TYPICAL TRANSFER CURVE FOR A INVERTING GATE AT VDD = 10V Noise margin is the difference between the noise-immunity voltage (VIL or VIH) and the output voltage VO. Noise margin voltage is the maximum voltage that can be impressed upon 2. Output short circuits often result from testing errors or im- an input voltage VIN (where VIN is the VOL or VOH voltage of proper board assembly. Shorts on buffer outputs or the preceding stage) at any (or all) logic I/O terminals withacross power supplies greater than 5V can damage out upsetting the logic or causing any output to exceed the CMOS devices. output voltage (VO) conditions specified for VIL and VIH ratings. Figure 5 illustrates the noise margin concept in a sim3. CMOS, like active pull-up TTL, can be connected in the ple system. Minimum noise margins for buffered B-series "wire-OR" configuration because an "on" PMOS and an CMOS devices are 1V, 2V, and 2.5V, respectively, for supply "on" NMOS transistor could be directly shorted across the voltages 5V, 10V, and 15V. power supply rails. (Exception: CD40107B) 4. Paralleling inputs and outputs of gates is recommended only when the gates are within the same IC package. 5. Output loads should return to a voltage within the supply voltage range VDD to VSS . VDD = 5V VIH = 3.5V VOL = 0.5V VNML = 1V VIL = 1.5V VOH = 4.5V VNML = 1V VIH = 3.5V VOL = 0.5V 6. Large capacitive loads (greater than 5000pF) on CMOS buffers or high current drivers act like short circuits and may over dissipate output transistors. FIGURE 5. NOISE MARGIN EXAMPLE USING INVERTERS 5-5 Technical Overview Of the two noise limitation specifications (noise immunity and noise margin), noise immunity is more practical for CMOS devices because CMOS outputs are normally within 50mV of supply rails. Noise immunity increases as the input pulse width becomes less than the propagation delay of the circuit. This condition is often described as AC noise immunity. Further information on noise immunity is given in Application Note AN6587, "Noise Immunity of B-series CMOS Integrated Circuits". See Section 8, "How to Use AnswerFAX", in this selection guide. Clock Rise and Fall Time Requirements Most CMOS clocked devices have maximum rise and fall time ratings (normally 5ms to 15ms). With longer rise or fall times, a device may not function properly because of data www..com ripple through, false triggering problems, etc. Some B-series CMOS counters have Schmitt-trigger shaping circuits built into the clock circuit, removing the restriction for input rise or fall times. Long rise and fall times on CMOS buffer-type inputs cause increased power dissipation which may exceed device capability for operating power supply voltages greater than 5V. Parallel Clocking Process variations leading to differences in input threshold voltage among random device samples can cause loss of data between certain synchronously clock sequential circuits, as shown in Figure 6. This problem can be avoided if the maximum clock rise time (tRCL) for cascading any two CMOS sequential devices is limited in accordance with the following equation: B-Series Types 0.8V DD ( V ) Maximum t R C L = ------------------------------- x t P ( ns ) 1.15V Three-State Logic Three-state logic can be easily implemented by use of a transmission gate in the output circuit; this technique provides a solution to the wire-OR problem in many cases. Chip Assembly and Storage Harris CMOS integrated circuits are provided in a chip from (H suffix) to allow customer design of special and complex circuits to suit individual needs. CMOS chips are electrically identical to and offer the features of their counterparts sealed in ceramic and plastic packages. The following paragraphs describe mounting considerations, packaging, shipping and storage criteria, handling criteria, visual inspection criteria, testing criteria, and bonding pad layout and dimensions for each chip. Mounting Considerations All CMOS chips are non-gold backed and require the use of epoxy mounting, conductive silver paste or equivalent is recommended. In any case the manufacturer's recommendations for storage and use should be followed. In CMOS circuits MOS-transistor P-channel substrates (Ntype bulk material) are connected to VDD , therefore, when chips are mounted and a conductive paste is used, care must be taken to keep the active substrate isolated from ground or other circuit elements. Packing, Shipping, and Storage Criteria Solid-state chips, being small in size and unencapsulated, are physically fragile and require special handling consideration as follows: * Chips must be stored under proper conditions to insure that they are not subjected to a moist and/or contaminated atmosphere that could alter their electrical, physical, or mechanical characteristics. After the shipping container is opened, the chip must be stored under the following conditions: - Storage Temperature, 40oC Max - Relative Humidity, 50% Max - Clean, Dust-Free Environment * The user must exercise proper care when handling chips to prevent even the slightest physical damage to the chip. * During mounting and lead bonding of chips the user must use proper assembly techniques to obtain proper electrical, thermal, and mechanical performance. where tP = tPHL or tPLH (whichever is smaller) for the unit A in Figure 6 as specified on the device data sheet at the specified value of VDD and loading conditions. Schmitt-trigger circuits such as the CD4093B are an ideal solution to applications requiring wave-shipping. D A Q1 D Q2 B CL 0.7VDD CL Q1 SWITCHING POINT = 0.3VDD Q2 NOTE: CASCADING WITH SLOW CLOCK CAN CAUSE ERROR 0.3VDD VDD PROPER SWITCHING POINT = 0.7VDD ERROR * After the chip has been mounted and bonded, any necessary procedure must be followed by the user to insure that these non-hermetic chips are not subjected to a moist and contaminated atmosphere which might cause the development of electrical conductive paths across the relatively small insulating surfaces. In addition, proper consideration must be given to the protection of these devices from other harmful environments which could conceivably affect their performance and/or reliability. Handling Criteria The user should find the following suggested precautions helpful in handling CMOS chips. FIGURE 6. ERROR EFFECT THAT RESULTS FROM A SLOW CLOCK IN CASCADED CIRCUITS 5-6 Technical Overview Because of the extremely small size and fragile nature of chips, the equipment designer should exercise care in handling these devices. For additional handling considerations for CMOS devices, refer to Application Note AN6525, "Guide to Better Handling and Operation of CMOS Integrated Circuits". See Section 8, "How to Use AnswerFAX", in this selection guide. * Grounding - Bonders, pellet pick-up tools, table tops, trim and form tools, sealing equipment, and other equipment used in chip handling should be properly grounded. - The operator should be properly grounded. * In-Process Handling - Assemblies or subassemblies of chips should be transwww..com ported and stored in conductive carriers. - All external leads of the assemblies or subassemblies should be shorted together. * Bonding Sequence - Connect VDD first to external connections, for example, terminal 14 of the CD4001BH. - Remaining functions may be connected to their external connections in any sequence. * Testing - Transport all assemblies of chips in conductive carriers. - In testing chip assemblies or subassemblies, the operator should be properly grounded. Visual Inspection Criteria All standard commercial CMOS chips undergo a visual inspection which is patterned after MIL-STD-883, Method 2010, Condition B with modifications reflecting CMOS requirements. Testing Criteria CMOS chips are DC electrically tested 100% in accordance with the same standards prescribed for Harris devices in standard packages. Device Testing Harris CMOS circuits are 100% tested by circuit probe in the wafer stage and are 100% tested again after they have been packaged. DC tests of Harris devices are performed at 5V, 10V, 15V, and 20V; functionality is checked at 2.8V, 17V, and 20V. Sample testing is used to assure adherence to quality requirements and AC specifications. Static test, high speed functional and DC parametric tests, are performed at wafer and package stages by means of a Teradyne 325 test set or equivalent. Users should follow the sequences below when testing CMOS devices: 1. Insert the device into the test socket. 2. Apply VDD. 3. Apply the input signal. 4. Perform the test. 5. On completion of test, remove the input signal. 6. Turn off the power supply (VDD). 7. Remove the device from the test socket and insert it into a conductive carrier. CMOS devices under test must not be exposed to electrostatic discharge or forward biasing of the intrinsic protective diodes shown in Figure 3. Detailed information on the techniques employed in the testing of Harris CMOS integrated circuits are described in Application Note AN6532, "Fundamentals of Testing CMOS Integrated Circuits". See Section 8, "How to Use AnswerFAX", in this selection guide. Device Mounting Integrated circuits are normally supplied with lead-tin plated leads to facilitate soldering into circuit boards. In those relatively few applications requiring welding of the device leads, rather than soldering, the devices may be obtained with nickel-plated Kovar leads (See MIL-I-38535). It should be recognized that this type of plating will not provide complete protection against lead corrosion in the presence of high humidity and mechanical stress. In any method of mounting integrated circuits which involves bending or forming of the device leads, it is extremely important that the lead be supported and clamped between the bend and the package seal, and that bending be done with care to avoid damage to lead plating. In no case should the radius of the bend be less than the diameter of the lead. It is also extremely important that the ends of bent leads be straight to assure proper insertion through the holes in the printed-circuit board. High Voltage B-Series CMOS Integrated Circuits Harris CD4000B series types have a maximum DC supply voltage rating of -0.5V to 20V, and a recommended operating supply voltage range of 3V to 18V. The major features of this series are as follows: * High Voltage (20V) Ratings * 100% Tested for Quiescent Current at 20V * 5V, 10V, and 15V Parametric Ratings * Standardized, Symmetrical Output Characteristics * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC * Noise Margin (Full Package Temperature Range) = 1V at VDD = 5V 2V at VDD = 10V 2.5 V at VDD = 15V * Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of B-Series CMOS Devices". JEDEC Minimum Standard Under the sponsorship of the Joint Electron Devices Engineering Council (JEDEC) of the Electronic Industries Association (EIA), minimum industrial standards have been established for the maximum ratings, DC and AC electrical 5-7 Technical Overview characteristics of B-series CMOS integrated circuits. The JEDEC standard (JEDEC Tentative Standard No. 13B) defines B-series CMOS integrated circuits as a uniform family of both buffered and unbuffered types that have an absolute DC supply voltage rating of at least 18V. Buffered CMOS Devices These are types in which the output "on" impedance is independent of any and all valid input logic conditions, both preceding and present. All such CMOS products are designated by suffix "B" following the basic type number. Unbuffered CMOS Devices These are types that meet all B-series specifications except that the logical outputs are not buffered and the noise-immunity voltages, VIL and VIH, are specified as 20% and 80%, www..com respectively, of VDD for operation from 5V, 10V, and 17V and 83%, respectively, of VDD for operation from 15V. All such CMOS product are designated by the suffix "UB". The JEDEC minimum standard also includes in the B-series, CMOS types that have analog inputs or outputs and in addition, have maximum ratings and logical input and output parameters that conform to B-series specifications wherever applicable. These CMOS devices are also designated by the suffix "B". All B-series CMOS devices can directly replace their A-series counterparts in most applications. The UB types are high voltage versions of corresponding A-series (unbuffered) types. Commercial A-series types have been obsoleted and replaced by B-series counterparts with only a few exceptions such as the continuing CD4059A types. The Absolute Maximum Rating - JEDEC table lists the minimum standards established for the maximum ratings and recommended operating conditions for B-series CMOS integrated circuits. The DC Electrical Specification - JEDEC table shows the JEDEC standards for the DC electrical specifications of CMOS B-series integrated circuits. Standardized Ratings and Static Characteristics Harris B-series CMOS integrated circuits meet or exceed the most stringent requirements of the JEDEC B-series specifications. The Absolute Maximum Ratings table shows the standardized maximum ratings and recommended operating supply voltage range for Harris B-series CMOS integrated circuits. The standardized DC electrical specifications for these devices are shown in the DC Electrical Specification table. As with the JEDEC specifications, the Harris standardized characteristics classify the B-series devices into three leakage (quiescent device current) categories. Table 1 lists the Harris types in each category and indicates types that, although they are still B-series types, differ in one or more static characteristics. The Absolute Maximum Ratings table and the DC Electrical Specification table show that in a number on important respects, Harris has established new performance standards for B-series CMOS logic circuits. * Tight Limits For All Packages Harris devices used the same set of limits for all package styles. The JEDEC standard establishes two sets of limits for most DC parameters; a tight set for products having a full operating temperature range of -55oC to +125oC (all Harris devices), and a relaxed set for products having a limited temperature range of -40oC to +85oC. Because Harris supplies only one premium grade of B-series product in all package styles (i.e., fall-out chips are not used), all B-series CMOS devices are specified to the tight set of limits only. * Improved Voltage Rating All Harris B-series devices are tested to voltages that insure safe operation at the absolute maximum DC supply voltage rating of 20V. This higher rating permits greater derating for reliable 15V operation, permits greater 15V supply tolerance and peak transients, and permits system use to 18V with confidence. * Wider Operating Range All Harris B-series devices have a recommended maximum operating voltage of 18V. The higher limit permits 18V system supply operation, and also permits wider power source tolerance and transients for supplies normally set up to 18V * Lower Leakage Current The JEDEC standard establishes three sets of limits for quiescent device current (IDD) intended to match chip complexity to device leakage current as realistically as possible. For all three levels of chip complexity, all Harris B-series devices (regardless of package) conform to the tighter set of limits established in the standard. In addition, a maximum rating is specified at 20V, as well as at 5V, 10V, and 15V. As a result: - In current limited applications, CMOS users can depend on one tight leakage limit independent of package style selected. - Customer use of CMOS product up through 18V is protected by a published tight leakage current specification at 20V (as well as by an input leakage specification at 18V). * Symmetrical Output Most Harris B-series devices have balanced complementary output drive (i.e., the output high current IOH rating is the same as the output low current IOL rating specified to the tighter set of limits established in the JEDEC standard. The balanced output provides uniform rise and fall time performance, improved system noise energy (dynamic) immunity, optimum device speed for both output switching low-to-high (tPLH) and output switching high-to-low (tPHL), and in general the identical high and low DC and AC characteristics normally associated with a good complementary output drive circuit. MOS system design, simulation, and performance are significantly enhanced by equal high and low DC and AC performance ratings and one tight specification limit for all package styles. 5-8 Technical Overview * Improved Input Current (Leakage) Ratings All Harris B-series devices (regardless of package) have a maximum input leakage current (IIN) rating of 100nA specified at voltages up to 18V, and a maximum limit of 1A at the upper limit of the package temperature range. Actually, the 100nA rating is a practical specification limited by the inability of commercial test equipment to measure lower currents. Laboratory tests show that input leakage currents of Harris B-series CMOS devices are significantly lower than this limit, typically ranging from 10pA to 100pA. * Buffered and Unbuffered Gates The new industry standard establishes a suffix "UB" for CMOS products that meet all B-series specifications except that the logical outputs of the devices are not buffered www..com and the VIL and VIH specifications are relaxed. The suffix "B" defines only buffered output devices in which the output "on" impedance is independent of any and all valid input logic conditions, both preceding and present. Harris supplies both buffered "B" and unbuffered "UB" versions of a few popular NOR and NAND gates to make available to designers the advantages of both. The following table briefly compares the features of the two versions, a more detailed coverage of the special features of B- and UB- series CMOS gates is provided by Application Note AN6558, "Understanding Buffered and Unbuffered CMOS Characteristics". See Section 8, "How to Use AnswerFAX", in this selection guide. IOL , OUTPUT LOW (SINK) CURRENT (mA) COMPARISON OF "B" AND "UB" BUFFERED VERSION "B" Moderate Excellent Constant High Yes Low UNBUFFERED VERSION "UB" Fast Good Variable Medium No High CHARACTERISTIC Propagation Delay (Speed) Noise Immunity/Margin Output Impedance and Output Transition Time AC Gain Output Oscillation for Slow inputs Input Capacitance * Reliability Harris B-series CMOS integrated circuits incorporate the latest improvements in processing technology and plastic and ceramic packaging techniques. Product quality is real time controlled using accelerated temperature group quality screening in which measured DC parameters are criticized against tight B-series limits. Figure 7 through Figure 10 show the standardized N- and P-channel drain characteristics for B-series CMOS devices, and Figure 11 through Figure 14 show the normalized variation of output source and sink currents with respect to temperature and voltage in these devices. IOL , OUTPUT LOW (SINK) CURRENT (mA) 35 30 25 20 15 10 5V 5 0 AMBIENT TEMPERATURE, TA = 25oC 5 10 15 20 VDS , DRAIN-TO-SOURCE VOLTAGE (V) 10V GATE-TO-SOURCE VOLTAGE, VGS = 15V 15 12.5 10 7.5 5 2.5 0 GATE-TO-SOURCE VOLTAGE, VGS = 15V 10V 5V AMBIENT TEMPERATURE, TA = 25oC 5 10 15 20 VDS , DRAIN-TO-SOURCE VOLTAGE (V) FIGURE 7. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 8. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 0 IOH , OUTPUT HIGH (SOURCE) CURRENT (mA) GATE-TO-SOURCE VOLTAGE, VGS = -5V -5 -10 -15 -10V -20 -25 -15V -30 AMBIENT TEMPERATURE, TA = 25oC -20 -15 -10 -5 VDS , DRAIN-TO-SOURCE VOLTAGE (V) FIGURE 9. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 5-9 Technical Overview 0 AMBIENT TEMPERATURE, TA = 25oC GATE-TO-SOURCE VOLTAGE, VGS = -5V -5 IOH, OUTPUT HIGH (SOURCE) CURRENT (mA) NORMALIZED SINK, IOL , AND SOURCE, IOH , CURRENT 2 -10V -10 1 -15V -15 -20 -15 -10 -5 VDS , DRAIN-TO-SOURCE VOLTAGE (V) -100 -50 0 50 100 150 TA, AMBIENT TEMPERATURE (oC) www..com FIGURE 10. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 11. VARIATION OF NORMALIZED OUTPUT LOW (SINK) CURRENT IOL AND OUTPUT HIGH (SOURCE) CURRENT IOH WITH TEMPERATURE 1.4 NORMALIZED SINK, IOL , AND SOURCE, IOH , CURRENT 1.2 1 0.8 0.6 0.4 0.2 0 5 10 15 VDD , SUPPLY VOLTAGE (V) NORMALIZED TRANSITION TIME, tTHL , tTLH , AND PROPAGATION DELAY TIME, tPHL , tPLH 1.4 1.2 1 0.8 0.6 -100 -75 -50 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) FIGURE 12. VARIATION OF NORMALIZED OUTPUT LOW (SINK) CURRENT IOL AND OUTPUT HIGH (SOURCE) CURRENT IOH WITH SUPPLY VOLTAGE FIGURE 13. VARIATION OF LOW-TO-HIGH (tTLH) AND HIGH-TOLOW (tTHL) TRANSITION TIME, AND LOW-TO-HIGH (tPHL) PROPAGATION DELAY TIME WITH TEMPERATURE NORMALIZED LOW-TO-HIGH, tTLH , AND HIGH-TO-LOW , tTHL , TRANSITION TIME tTHL , tTLH , TRANSITION TIME (ns) 4 3.5 3 2.5 2 1.5 1 0.5 AMBIENT TEMPERATURE, TA = 25oC AMBIENT TEMPERATURE, TA = 25oC 200 VDD, SUPPLY VOLTAGE = 5V 150 100 50 10V 15V 0 2 4 6 8 10 12 14 16 0 20 40 60 80 100 VDD , SUPPLY VOLTAGE (V) CL , LOAD CAPACITANCE (pF) FIGURE 14. VARIATION OF LOW-TO-HIGH (tTLH) AND HIGH-TOLOW (tTHL) TRANSITION TIME WITH SUPPLY VOLTAGE FIGURE 15. VARIATION OF TRANSITION TIME (tTHL, tTLH) WITH LOAD CAPACITANCE 5-10 Technical Overview B-Series AC Electrical Specifications B-series AC electrical specifications for individual types are under the following conditions: VDD = 5V, 10V, and 15V; TA = +25oC; CL = 50pF; RL = 200k; tR and tF = 20ns. Figure 13 shows the variation of B-series AC parameter with temperature. Figure 14 shows the variation of output transition time with supply voltage. Figure 17 shows the variation of the standardized output transition time with load capacitance. Maximum propagation delay or transition times for values of CL other than the specified 50pF can be determined by use of the multiplication factor (usually 2) between the typical and maximum values given in the AC specifications chart included in the technical data for each device applied to the typical curves, and also shown in the device technical data. www..com 20ns OUTPUT DISABLE 90% 50% tPLZ OUTPUT LOW TO OFF tPHZ OUTPUT HIGH TO OFF OUTPUTS CONNECTED 90% 50% 10% OUTPUTS DISCONNECTED VSS OUTPUTS CONNECTED 10% tPZL 90% 50% 10% tPZH VOL VOH 20ns VDD VSS VDD B-Series AC Switching Specifications The AC Electrical Specification table defines the major CMOS AC specifications, with reference to the waveforms shown in Figure 16 through Figure 19. Test conditions of VDD , low capacitance (CL), and input conditions are given for individual types in the published data. CMOS Special Products Harris supplies some special CMOS products that have operating supply voltage ranges and other characteristics that differ from the standardized data specified for B-series CMOS integrated circuits. These special application types include: interface circuits for level shifting applications to interface CMOS logic levels with different logic types; display drivers non-multiplexed, 4 digit, 7 segment LCD types containing all the circuitry necessary for driving conventional LCD displays without the need for external components, and a video sync generator function. tR INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tF VDD OTHER INPUTS FIGURE 18A. OUTPUT DISABLE IC WITH THREESTATE OUTPUT OUTPUT RL = 1k CL 50pF VDD FOR tPLZ AND tPZL VSS FOR tPHZ AND tPZH FIGURE 18B. FIGURE 18. THREE-STATE PROPAGATION DELAY WAVE SHAPES AND TEST CIRCUIT tRCL CLOCK INPUT 90% 10% tH(H) (NOTE 1) DATA INPUT tSU(H) (NOTE 1) tFCL VDD 50% GND tH(L) (NOTE 1) 50% GND tSU(L) (NOTE 1) tTLH tTHL 90% 50% 10% tPHL GND VDD tTHL VDD 50% 50% INVERTING OUTPUT VDD GND OUTPUT 90% FIGURE 16. TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tRCL CLOCK 90% 10% tFCL tWL + tWH = 1 fCL VDD 50% 10% tWL 50% 50% GND tWH VDD tREM 50% tPLH SET, RESET OR PRESET GND NOTE: 1. (H) or (L) Optional FIGURE 19. SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS NOTE: Outputs should be switching from 10% VDD to 90% VDD in accordance with the device truth table. FIGURE 17. CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH 5-11 Family Ratings and Specifications Absolute Maximum Ratings JEDEC Standard for DC Specifications of B-Series CMOS Integrated Circuits (Note 1 and Note 2) DC Input Current, IIN (For Any One Input). . . . . . . . . . . . . . . . . . 10mA Storage Temperature, TS . . . . . . . . . . . . . . . . . . . . -65oC to +150oC DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . -0.5V to +18V DC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . +3V to +15V Operating Temperature Range, TA . . . . . . . . . . . . . -55oC to +125oC DC Electrical Specification www..com PARAMETERS Quiescent Device Current Gates SYMBOL IDD JEDEC Standard for DC Specifications of B-Series CMOS Integrated Circuits (NOTE 3) TLOW MIN 4.95 9.95 14.95 MAX 0.25 0.5 1 1 2 4 1 2 4 4 8 16 5 10 20 20 40 80 0.05 0.05 0.05 MIN 4.95 9.95 14.95 (NOTE 4) THIGH MAX 0.25 0.5 1 1 2 4 1 2 4 4 8 16 5 10 20 20 40 80 0.05 0.05 0.05 MIN 4.95 9.95 14.95 MAX 7.5 15 30 7.5 15 30 30 60 120 30 60 120 150 300 600 150 300 600 0.05 0.05 0.05 UNIT A A A A A A A A A A A A A A A A A A V V V V V V +25oC TYP - TEST CONDITIONS VIN = VSS or VDD All Valid Input Combinations TEMP. RANGE Mil VDD (V) 5 10 15 Comm 5 10 15 Buffers, Flip-Flops IDD VIN = VSS or VDD All Valid Input Combinations Mil 5 10 15 Comm 5 10 15 MSI IDD VIN = VSS or VDD All Valid Input Combinations Mil 5 10 15 Comm 5 10 15 Low Level Output Voltage VOL VIN = VSS or VDD |IO| <1A All 5 10 15 High Level Output Voltage VOH VIN = VSS or VDD |IO| <1A All 5 10 15 For specific technical information on each individual device type, refer to the appropriate data sheet in Harris AnswerFAX. See Section 8, "How to use AnswerFAX", in this selection guide. 5-12 Family Ratings and Specifications DC Electrical Specification JEDEC Standard for DC Specifications of B-Series CMOS Integrated Circuits (Continued) (NOTE 3) TLOW MIN 3.5 7 11 4 8 12.5 0.64 1.6 4.2 0.52 1.3 3.6 -0.25 -0.62 -1.8 -0.2 -0.5 -1.4 MAX 1.5 3 4 1 2 2.5 0.1 0.3 0.4 1.6 MIN 3.5 7 11 4 8 12.5 0.51 1.3 3.4 0.44 1.1 3.0 -0.2 -0.5 -1.5 -0.16 -0.4 -1.2 (NOTE 4) THIGH MAX 1.5 3 4 1 2 2.5 0.1 0.3 0.4 1.6 7.5 MIN 3.5 7 11 4 8 12.5 0.36 0.9 2.4 0.36 0.9 2.4 -0.14 -0.35 -1.1 -0.12 -0.3 -1.0 MAX 1.5 3 4 1 2 2.5 1 1 12 12 UNIT V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA A A A A pF +25oC TYP - PARAMETERS Input Low Voltage B Types SYMBOL VIL TEST CONDITIONS VO = 0.5V or 4.5V VO = 1V or 9V VO = 1.5V or 13.5V |IO| <1A TEMP. RANGE All VDD (V) 5 10 15 5 10 15 UB Types www..com Input High Voltage B Types VIH VO = 0.5V or 4.5V VO = 1V or 9V VO = 1.5V or 13.5V |IO| <1A All 5 10 15 5 10 15 UB Types Output Low (Sink) Current IOL VO = 0.4V VIN = 0V or 5V VO = 0.5V VIN = 0V or 10V VO = 1.5V VIN = 0V or 15V Mil 5 10 15 Comm 5 10 15 Output High (Source) Current IOH VO = 4.6V VIN = 0V or 5V VO = 9.5V VIN = 0V or 10V VO = 13.5V VIN = 0V or 15V Mil 5 10 15 Comm 5 10 15 Input Current IIN VIN = 0V or 15V VIN = 0V or 15V Mil Comm Mil Comm All 15 15 15 15 - Three-State Output Leakage Current Input Capacitance Per Unit Load NOTES: IOUT Max VIN = 0V or 15V VIN = 0V or 15V CIN Any Input 1. Voltages referenced to VSS . 2. Reprinted from JEDEC Standard No. 13-B, "JEDEC Standard Specification for Description of B-Series CMOS Devices". 3. TLOW = -55oC for Military Temperature Range Device, -40oC for Commercial Temperature Device (All Harris Devices). 4. THIGH = +125oC for Military Temperature Range Device, +85oC for Commercial Temperature Range Device. For specific technical information on each individual device type, refer to the appropriate data sheet in Harris AnswerFAX. See Section 8, "How to use AnswerFAX", in this selection guide. 5-13 Family Ratings and Specifications Standardized Absolute Maximum Ratings For B-Series CMOS Integrated Circuits Power Dissipation Per, PD TA = -55oC to +100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW TA = +100oC to +125oC . . . Derate Linearly at 12mW/oC to 200mW Device Dissipation Per Output Transistor For TA = Full Package Temperature Range (All Package Test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range, TA . . . . . . . . . . . . . -55oC to +125oC Storage Temperature, TSTG . . . . . . . . . . . . . . . . . . -65oC to +150oC DC Supply Voltage, VDD Voltage Reference to VSS Terminal. . . . . . . . . . . . . -0.5V to +20V Input Voltage, All Inputs . . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, For Any One Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Lead Temperature (During Soldering) At Distance 1/16in. 1/32in. (1.59mm 0.79mm) from Case for 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions Supply, Voltage Range For TA = Full Package Temperature Range . . . . . . . +3V to +18V www..com Standardized DC Electrical Specification For B-Series CMOS Integrated Circuits LIMITS +25oC TEST CONDITIONS VO (V) Gates, Inverters (Note 1) Buffers, FlipFlops, Latches, Multi-Level Gates (MSI-1 Types) (Note 1) Complex Logic (MSI-2 Types) (Note 1) Output Low (Sink) Current Min IOL Min 0.4 0.5 1.5 Output High (Source) Current, Min IOH Min 4.6 2.5 9.5 13.5 VIN (V) 0, 5 0, 10 0, 15 0, 20 0, 5 0, 10 0, 15 0, 20 0, 5 0, 10 0, 15 0, 20 0, 5 0, 10 0, 15 0, 5 0, 5 0, 10 0, 15 VDD (V) 5 10 15 20 5 10 15 20 5 10 15 20 5 10 15 5 5 10 15 PARAMETERS Quiescent Device Current SYMBOL IDD Max -55oC 0.25 0.5 1 5 1 2 4 20 5 10 20 100 0.64 1.6 4.2 -6.4 -2 -1.6 -4.2 -40oC 0.25 0.5 1 5 1 2 4 20 5 10 20 100 0.61 1.5 4 -0.61 -1.8 -1.5 -4 +85oC 7.5 15 30 150 30 60 120 600 150 300 600 3000 0.42 1.1 2.8 -0.42 -1.3 -1.1 -2.8 +125oC 7.5 15 30 150 30 60 120 600 150 300 600 3000 0.36 0.9 2.4 -0.36 -1.15 -0.9 -2.4 MIN 0.51 1.3 3.4 -0.51 -1.6 -1.3 -3.4 TYP 0.01 0.01 0.01 0.02 0.02 0.02 0.02 0.04 0.04 0.04 0.04 0.08 1 2.6 6.8 -1 -3.2 -2.6 -6.8 MAX 0.25 0.5 1 5 1 2 4 20 5 10 20 100 - UNIT A A A A A A A A A A A A mA mA mA mA mA mA mA For specific technical information on each individual device type, refer to the appropriate data sheet in Harris AnswerFAX. See Section 8, "How to use AnswerFAX", in this selection guide. 5-14 Family Ratings and Specifications Standardized DC Electrical Specification For B-Series CMOS Integrated Circuits (Continued) LIMITS +25oC TEST CONDITIONS VO (V) Output Voltage High-Level www..com Input Low Voltage VIL Max VOH Min 0.5, 4.5 1, 9 B Types UB Types 1.5, 13.5 0.5, 4.5 1, 9 1.5, 13.5 Input High Voltage VIH Max 0.5, 4.5 1, 9 B Types UB Types 1.5, 13.5 0.5, 4.5 1, 9 1.5, 13.5 Input Current Three-State Output Leakage Current NOTE: 1. Classifications of Harris CMOS B-Series Types are Shown in Table 1. IIN Max IOUT Max 0, 18 VIN (V) 0, 5 0, 10 0, 15 0, 5 0, 10 0, 15 0, 18 0, 18 VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 18 18 0.1 0.4 PARAMETERS Output Voltage LowLevel SYMBOL VOL Max -55oC -40oC +85oC 0.05 0.05 0.05 4.95 9.95 +125oC MIN 4.95 9.95 14.95 3.5 7 11 4 8 12.5 TYP 0 0 0 5 10 15 10-5 10-4 MAX 0.05 0.05 0.05 1.5 3 4 1 2 2.5 0.1 0.4 UNIT V V V V V V V V V V V V V V V V V V A A 14.95 1.5 3 4 1 2 2.5 3.5 7 11 4 8 12.5 0.1 0.4 1 12 1 12 - For specific technical information on each individual device type, refer to the appropriate data sheet in Harris AnswerFAX. See Section 8, "How to use AnswerFAX", in this selection guide. 5-15 Family Ratings and Specifications AC Electrical Specifications Definitions SYMBOL MIN MAX NOTES PARAMETERS PROPAGATION DELAY Outputs Going High to Low Outputs Going Low to High OUTPUT TRANSITION TIME Outputs Going High to Low Outputs Going Low to High PULSE WIDTH Set, www..com Reset, Preset, Enable, Disable, Strobe, Clock Clock Input Frequency Clock Input Rise and Fall Time Set-Up Time Hold Time Removal Time - Set, Reset, Preset-Enable THREE-STATE DISABLE DELAY TIMES High Level to High Impedance High Impedance to Low Level Low Level to High Impedance High Impedance to High Level NOTES: tPHL tPLH - X X - tTHL tTLH - X X - tWL or tWH fCL tRCL, tFCL tSU tH tREM X X X X X X - 1 1, 2 1 1 1 tPHZ tPZL tPLZ tPZH - X X X X - 1. By placing a defining Min or Max in front of definition, the limits can change from Min to Max, or vice versa. 2. Clock input waveform should have a 50% duty cycle and be such as to cause the Outputs to be switching from 10% VDD to 90% VDD in accordance with the device truth table. TABLE 1. CLASSIFICATION OF HARRIS B-SERIES CMOS INTEGRATED CIRCUITS ACCORDING TO CIRCUIT COMPLEXITY BUFFERS/FLIP-FLOP/ LATCHES/MULTI-LEVEL GATES (MSl-1) CD4009UB (Note 1) CD4010B (Note 1) CD4013B CD4019B CD4027B C04093B CD4006B GATES/INVERTERS CD4001B CD4069UB COMPLEX LOGIC (MSI-2) CD4055B (Note 1) CD4056B (Note 1) CD4060B CD4063B CD4067B (Note 1) CD4076B CD4089B CD4532B CD4001UB CD4070B CD4095B CD4008B CD4536B CD4002B CD4007UB CD4011B CD4071B CD4072B CD4073B CD4096B CD4098B CD4502B (Note 1) CD4503B CD4504B CD4014B CD4015B CD4017B CD4541B CD4543B CD4555B CD4011UB CD4012B CD4075B CD4077B CD4030B CD4041UB (Note 1) CD4018B CD4020B CD4556B CD4560B For specific technical information on each individual device type, refer to the appropriate data sheet in Harris AnswerFAX. See Section 8, "How to use AnswerFAX", in this selection guide. 5-16 Family Ratings and Specifications TABLE 1. CLASSIFICATION OF HARRIS B-SERIES CMOS INTEGRATED CIRCUITS ACCORDING TO CIRCUIT COMPLEXITY (Continued) BUFFERS/FLIP-FLOP/ LATCHES/MULTI-LEVEL GATES (MSl-1) CD4042B CD4519B CD4021B GATES/INVERTERS CD4016B (Note 1) CD4023B CD4078B COMPLEX LOGIC (MSI-2) CD4094B CD4566B CD4081B CD4043B CD40106B CD4022B CD4097B (Note 1) CD4099B CD4585B CD4025B CD4082B CD4044B CD40107B (Note 1) CD40109B (Note 1) CD40174B CD4024B CD4724B CD4048B www..com CD4066B (Note 1) CD4068B CD40117B CD4047B CD4026B CD4508B CD14538B CD4572UB CD4049UB (Note 1) CD4050B (Note 1) CD4085B CD4086B CD4028B CD4510B CD40100B CD40175B CD4029B CD4511B (Note 1) CD4512B CD4514B CD4515B CD40102B CD40257B CD4031B CD4033B CD4034B CD40103B CD40105B CD40110B (Note 1) CD40147B CD40160B CD40161B CD4035B CD4040B CD4045B (Note 1) CD4046B (Note 1) CD4051B (Note 1) CD4052B (Note 1) CD4053B (Note 1) CD4054B (Note 1) NOTE: CD4516B CD4517B CD4518B CD4520B CD40163B CD4521B CD40192B CD4522B CD40193B CD4527B CD40194B CD4529B 1. Indicates types for which, because of special design requirements, one or more static characteristics differ from the standardized data. Refer to data pages on these types for specific differences. 5-17 Enhanced Product STANDARD IC CIRCUITS SUFFIX "X" Burn-In Time (Note 1) Temperature (Note 1) Bias Voltage CD4000B Special 160 Hours 100% BURN-IN 160 HRS AT +125oC OR EQUIVALENT PRODUCT FLOW STANDARD PRODUCT +125oC 15V 100% PARAMETRIC AND FUNCTIONAL TESTS AT +25oC Differs by Type PRODUCT IDENTIFICATION All Enhanced Product is Identified by a Suffix "X" www..com Examples: Standard CD4001BE NOTE: 1. Or equivalent means equivalent time-temperature /voltage resulting in the same activation energy. ENHANCED PRODUCT SAMPLE PARAMETRIC AND FUNCTIONAL TESTS AT +25oC AQL = 0.025% Enhanced CD4001BEX = PRODUCT STATE OR PROCESS = QUALITY ASSURANCE STEP 5-18 |
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